Failed Abstractions - the Verilog always block Aug 5, 2020 Hardware Modeling Verilog Verilog is a hardware description language (HDL) widely used in both academia and industry. Its purpose is to provide an abstraction over using the particular logic gates of any one library by offering description capabilities on the register-transfer-level (RTL). This post discusses two language features that failed to abstract in a meaningful way and instead intermingle distinct concepts: The always block which can infer combinational logic, latches or registers, and the reg keyword which can be used to either declare register elements or transfer elements depending on the usage of the element within an always-block. ...
Test(ing) Post Jul 24, 2020 Introduction This is a short test post to start this blog. But let’s just imagine this was a post about software testing instead. The Story Imagine a purely fictional story about my colleague Bob who always insisted on TDD and was fired for underperforming and my other colleague John who never wrote tests and was fired for deploying changes that bricked a production system. As always, the solution is to strike a balance between the extremes. ...